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This repository contains optimized **ROCmFP4** and **ROCmFP8** GGUF releases of **Qwen 3.8 27B**, custom-engineered for **AMD Strix Halo (Ryzen AI Max+ 395 / Radeon 8060S)** and **AMD Radeon discrete GPUs**. > 🛠️ **Unified HaloFPX Server:** github.com/julianmb/halofpx (Multi-model zoo, hot-swapping, OpenAI API) > 📖 **Qwen 3.8 Dedicated Deep-Dive:** github.com/julianmb/q38rocm (Standalone optimization report, benchmarks & tuning) Strix Halo features a **50 TOPS XDNA 2 NPU** (`/dev/accel/accel0`). Extensive empirical benchmarking demonstrates: - **Sustained Decode Ceiling:** **33.8 tok/s** via embedded MTP (iGPU only) is the practical ceiling. The NPU does *not* improve sustained decode speed. - **Proven NPU Value:** **1.8× faster first-token TTFT on long prompts (870 ms vs 1587 ms)** via hybrid NPU-burst → iGPU handoff (`scripts/run_pipeline.py`). - **See `docs/NPU_INTEGRATION.md`** for complete setup instructions.

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second-generation quant: same trunk type (iq4_xs), but calibrated with a 926-entry imatrix (1,024 chunks) via the ROCmFPX banded quantizer, and the 51B PLE lookup table **left at q8_0** (no `--tensor-type` cut). 5.56 bpw, 115 giB — 24 giB bigger than the 91g PLE file. pick M2 when you want the **best measured quality** and don't mind the 24 giB: at ≤32k plain it matches PLE, and at 32k MTP it measured fastest. for shallow-depth MTP speed take the 91g PLE; for deep 128k+ MTP the static 116g had a small in-sweep edge (17.4 vs 13.3/13.5 — within the same-config spread, n=1 caveat). every quant descends from an F16 that was byte-verified against the official `Qwen/Qwen3.8-Flash-Next-FP8` checkpoint: hyper-connection norms folded to (1 + w) (97/97 tensors — the converter bug that produces deterministic garbage is fixed in our pipeline), PLE fp8 scale applied, expert stacking identity probed 512x3, GDN v-head reorder checked. details: https://github.com/julianmb/haloq38flash

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